The invention relates to computer memory and input/output systems. More particularly, the invention relates to assignment of addresses to input/output devices to facilitate on-line addition or deletion of input/output devices and to allow input/output devices having n address bits to be mapped into a larger address space than the n address bits would allow.
In computer systems with input/output (xe2x80x9cI/Oxe2x80x9d) devices mapped into the normal processor address space (often referred to as the xe2x80x9csystem address spacexe2x80x9d), an assignment of addresses of each of the I/O devices in the system address space is generally required. Typically, an I/O device may include a programmable register to store its starting address in the system address space. In a multiple bus architecture system employing I/O bridges, the I/O bridges are in turn provided with similar flexibility in locating their respective addresses in the system address space.
Generally, since many small computer systems have a limited system address space, fixed addresses are not assigned to most I/O devices or bridges. Instead, as each I/O device and/or I/O bridge is discovered during the system initialization, i.e., during a xe2x80x9cboot-upxe2x80x9d process, a block of addresses is assigned to each discovered device and/or bridge, starting address of each address block closely following the block assigned to a previously discovered device and/or bridge.
Unfortunately, however, this dynamic assignment of I/O addresses at the system start-up often results in a fragmentation of the system address space when one or more I/O devices are xe2x80x9chot swappedxe2x80x9d, i.e., replaced while the system remains powered-up and after the system initializationxe2x80x94sometimes also referred to as on-line-replacement (OLR). For example, when an I/O device occupying an address block of a given size, e.g., a one megabyte (Mbyte) block, is removed from the system, and is replaced by another I/O device requiring a larger address size, e.g., two Mbyte, the new device cannot fit into the same address space formerly occupied by the device being replaced. In this case, a new block of address space must be assigned to the new I/O device, thus leaving the once occupied one Mbyte block unused. After hot swapping of a few I/O devices, there may be a number of unused memory blocks, thus causing the I/O space in the system memory to be fragmented, and a device may be prevented from being added even though there are sufficient free memory space.
For example, assume an I/O address space 100 in the system memory comprises a two gigabyte (Gbyte) block (starting at the address 80000000 (HEX), and ending at the address FFFFFFFF (HEX)), and was assigned dynamically to then existing I/O devices, device A, device B, device C and device D, at system start-up as shown in FIG. 1A. The device A occupies the 20000000 (HEX) block 101 starting at address 0xc3x9780000000 (HEX). The device B occupies the 1000 (HEX) block 102 starting at address 0xc3x97A000000 (HEX). The device C occupies the 1000 (HEX) block 103 starting at 0xc3x97A0001000 (HEX). Finally, the device D occupies the 3FFFF000 (HEX) block 105 starting at address 0xc3x97C0001000 (HEX). The 1FFFF000 (HEX) block 104 is left unassigned, i.e., is a free space.
Suppose now that the device B is removed on-line, i.e., hot swapped out, making the 1000 (HEX) block 102a available again as shown in FIG. 1B. Suppose further that it is desirable to add another device A to the system. As can be seen, although there is sufficient available memory space, i.e., the free blocks 102a and 104 together comprise a 20000000 (HEX) block sufficient to accommodate a device A, because there is no contiguous block having a size 2000000 (HEX), the second device A cannot be added.
The above described fragmentation of I/O memory space is wasteful of valuable system memory, and is thus inefficient.
Moreover, in most conventional systems, a direct map from the processor""s address to the device address is provided. Although a typical system memory is capable of being addressed with a large number of bits, e.g., 64 bits, most I/O devices typically have a smaller number of address bits, e.g., 32 bits. That is, the smaller address space of I/O devices are directly mapped from a portion of the processor""s address space for all I/O devices. Even in systems with multiple I/O buses, unique 32-bit I/O device addresses are used across all buses in the system.
However, unfortunately, this small number of I/O device address bits creates a limit of the total amount of I/O device space, e.g., to around 2 gigabytes (xe2x80x9cGBxe2x80x9d) for all practical purposes for 32-bit I/O device addresses. As the number of I/O buses increases, the I/O memory space for each bus in the system becomes smaller. For example, if 1024 (e.g., 232) I/O buses were possible in a 32-bit I/O device system, each bus may be allotted a portion of the memory that is as little as 2 MB. Some I/O devices, e.g., networking cards and most graphics cards, require a large address region, e.g., 16 MB or more, and thus cannot be accommodated in a small memory allotment afforded in a conventional system.
Thus, there is a need for a more efficient method and device for providing an I/O address mapping, which provides a convenient on-line replacement of various I/O devices having different memory capacity requirements without causing a fragmentation of I/O memory space in the system memory.
There is also a need for a more efficient method and device for providing an I/O address mapping, which provides a larger memory space for each of the I/O devices in the system than the number of address bits available from the I/O devices would allow.
In accordance with the principles of the present invention, a method of mapping an input/output address space into a system memory of a computing system having one or more input/output devices comprises providing the input/output address space within the system memory, the input/output address space being addressable by a (n+l)-bit processor view input/output address, each of n and l being an integer larger than 1, and translating the processor view input/output address to a n-bit I/O device view address to address the one or more input/output devices.
In addition, in accordance with the principles of the present invention, an apparatus for mapping an input/output address space in a computing system having one or more input/output devices comprises a system memory having the input/output address space stored therein, the input/output address space being addressable by a (n+l)-bit processor view input/output address, each of n and l being an integer larger than 1, and means for translating the processor view input/output address to a n-bit I/O device view address to address the one or more input/output devices.
In accordance with another aspect of the principles of the present invention, a computer system having one or more input/output devices comprises a system memory having an input/output address space stored therein, the input/output address space being addressable by a (n+l)-bit processor view input/output address, each of n and l being an integer larger than 1, and one or more host input/output bridges each addressing a corresponding group of one or more input/output buses, each of the one or more host input/output bridges configured to translate the processor view input/output address to a n-bit I/O device view address to address the one or more input/output devices.